A successive approximation ADC samples an analog input and compares it to the output of a digital-to-analog converter (DAC). Each bit in the digital input of the DAC is sequentially determined until the DAC output equals the sampled analog input. A capacitor digital-to-analog converter (CDAC) is the basic element in many ADC circuit designs because the CDAC can also perform a sample and hold on the input signal.
CDACs are commonly used, in particular, in successive approximation ADCs. Successive approximation ADCs systematically evaluate the analog input signal in N steps to produce an N-bit digital code. The analog signal is successively compared to the CDAC output to determine the digital code, beginning with the determination of the most significant bit (MSB) and progressing until the least significant bit (LSB) is determined. In each successive comparison, the analog signal is compared to the CDAC's output resulting from the previously approximated bits plus the bit currently being tested, where the current bit is kept at 1 only if the CDAC's output is less than the analog signal.
One of the disadvantages inherent to successive approximation ADCs is that each bit must be sequentially determined, which adversely increases the time required to perform the conversion, especially when compared to flash ADCs. This disparity exists because flash ADCs do not sequentially determine each bit, but rather simultaneously solve all of the bits. Although relatively small and low-power ADCs can be realized using successive approximation techniques, these ADCs tend to be relatively slow because they require many clock cycles to complete each analog-to-digital conversion. An increase in the rate of analog-to-digital conversion, however, can be achieved by reducing the number of clock cycles needed for each analog-to-digital conversion by using a multistage pipelined ADC.
Multistage pipelined architectures allow multiple stages to operate concurrently to provide a high throughput rate. A multistage pipelined ADC works by having a first stage solve the most significant m bits and pass the analog remainder to the following stage, which solves the remaining n-m bits. At any time, the first stage operates on the most recent sample, while the next stage operates on the residue from the previous samples, and so forth. A sample and hold circuit between the two stages allows the second stage to operate while the first stage begins solving the next input sample. Thus, in a two stage pipelined architecture, two input samples are converted at the same time, doubling the sampling rate without changing the total time required for a single conversion.
Moreover, the die area occupied by pipelined converters is small compared to the area occupied by flash converters because pipelined converters require fewer comparators than flash converters (and thus, less circuitry). In addition to the die area being small for pipelined converters, die area also is linearly related to the resolution of the conversion, because if the necessary accuracy can be achieved through calibration or trimming, the resolution of the pipelined converter can in turn be increased by adding stages to the end of the pipeline without increasing the number of clock phases required per conversion. In contrast, flash architecture requires an exponential, rather than a linear increase in area to increase resolution and may also require trimming or calibration for higher linearity (e.g., greater than 8 or 9 bit linearity).
Known techniques of implementing an n-bit two stage pipeline converter involve having a first stage solve the most significant m bits and passing the analog remainder to a second stage that solves the remaining n-m bits. A sample and hold amplifier between the two stages allows the second stage to operate while the first stage begins solving the next input sample. In this manner, two input samples are being converted at the same time, doubling the sampling rate without changing the total time required for a single conversion.
However, the pipelined successive approximation ADC described above typically suffers from poor integral non-linearity or often is slow due to a reference feedforward correction technique that sometimes is used. Furthermore, another significant disadvantage of the above described pipelined successive approximation ADC topology, and other existing pipeline topologies is the need for a precision gain amplifier between the stages. The precision gain amplifier is required because if an analog signal is passed to a subsequent stage with even a slight gain error, the ADC will exhibit linearity errors. Accordingly, an accurate gain stage requires a feedback amplifier with a very high open loop gain that is generally slower than other circuits in the ADC and limits the conversion rate.